A microprocessor is provided with a cache memory in order to hide an execution penalty for an access to an external memory. Furthermore, in a recent system provided with a microprocessor, in order to improve program execution performance, a multiprocessor system provided with a plurality of processor cores, and/or a processor capable of multithread processing for efficiently executing a plurality of programs with one processor are/is now being employed.
In a multiprocessor and/or a multithreading processor, a memory for executing a plurality of programs is often used by sharing a single memory space. Also in the case of the above-mentioned cache memory, a cache memory is not provided individually for each processor and/or each thread, but a single cache memory or cache memory system is often put to shared use.
Normally, a cache memory has a set associative configuration with a plurality of ways. When a program accesses a cache memory, whether an access address causes a cache hit or a cache miss is determined normally by accessing all the ways.
In a multiprocessor and/or a processor for performing multithread processing, there exists a method for allocating cache ways so as not to allow data cached by respective programs to affect the mutual programs. In this case, if a cache miss occurs, a way allocated to each program is refilled with data, and therefore, a way in which a cache hit occurs for each program has a high probability of being the allocated way.
Despite this, since a shared cache for caching a shared memory is used, hit/miss determination has to be performed on all the ways, and thus cache hit/miss determination performed by accessing all the ways results in wasteful power consumption state.
In order to reduce power consumption during a cache access, there exists a method for performing cache hit/miss determination only on a way accessed last time, or accessing only a data array for a way accessed last time (e.g., Patent Document 1). However, the effectiveness of this method is limited to the case where an address is sequentially changed such as instruction fetch. Further, in the case of a multiprocessor system and/or a processor for performing multithread processing, instruction fetch addresses and/or data access addresses for a program subjected to parallel processing might not be continuous, which results in insufficient achievement of effects.
Patent Document 1: Japanese Unexamined Patent Publication NO. 11-39216